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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The MC54/74HC574A is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be stored even when the outputs are not enabled. The HC574A is identical in function to the HCT374A but has the flip-flop inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HC574A is the noninverting version of the HC564. * * * * * Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 266 FETs or 66.5 Equivalent Gates
MC54/74HC574A
J SUFFIX CERAMIC PACKAGE CASE 732-03
1
20
20 1
N SUFFIX PLASTIC PACKAGE CASE 738-03
20 1
DW SUFFIX SOIC PACKAGE CASE 751D-04
ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW Ceramic Plastic SOIC
PIN ASSIGNMENT LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK OUTPUT ENABLE 2 3 4 5 6 7 8 9 11 1 PIN 20 = VCC PIN 10 = GND 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D7 GND 9 10 12 11 Q7 CLOCK NON- INVERTING OUTPUTS OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6
FUNCTION TABLE
3/97
(c) Motorola, Inc. 1997
II I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII III I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II I II II I I IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIII II I IIIIIIIIIIIIIII IIIIIIIIIIII
Design Criteria Value 66.5 1.5 5.0 Units ea ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product W pJ 0.0075 * Equivalent to a two-input NAND gate. 3-1
Inputs OE L L L H Clock D H L X X
Output Q H L No Change Z
L,H, X
X = Don't Care Z = High Impedance
REV 7
MC54/74HC574A
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I III I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I III I I I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIII III I I III I IIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I II IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
IIIIIIII I I I I IIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII III III I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package mW TstgIIIIIIIIIIIIII - 65 to + 150 Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) 260 300
_C _C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter
Min 2.0 0
Max 6.0
Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0 0 0
+ 125 1000 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
v 85_C v 125_C
1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4
Unit V
Minimum High-Level Input Voltage
Vout = VCC - 0.1 V |Iout| 20 A
v v v
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V |Iout| 20 A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH |Iout| 20 A Vin = VIH
V
|Iout| |Iout| |Iout|
v 2.4 mA v 6.0 mA v 7.8 mA v 2.4 mA v 6.0 mA v 7.8 mA
2.48 3.98 5.48 0.1 0.1 0.1
2.34 3.84 5.34 0.1 0.1 0.1
VOL
Maximum Low-Level Output Voltage
Vin = VIL |Iout| 20 A
v
V
Vin = VIL
|Iout| |Iout| |Iout|
0.26 0.26 0.26
0.33 0.33 0.33
MOTOROLA
3-2
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC574A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I III I I I I IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I
Guaranteed Limit Symbol Iin IOZ Parameter Test Conditions VCC V 6.0 6.0 - 55 to 25_C 0.1 0.5
v 85_C v 125_C
1.0 5.0 1.0 10
Unit A A
Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package)
ICC
Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 A
6.0
4.0
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I I II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I III I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIII I I II I I II I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I III I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I
Guaranteed Limit Symbol S bl IOZ Parameter P Test C di i T Conditions VCC V 6.0 - 55 to 25_C 0.5
v 85_C v 125_C
5.0 10 40 160
Unit Ui A
Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package)
Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND |Iout| = 0 A
ICC
6.0
4.0
A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol S bl fmax
Parameter P
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 60 2.0 3.0 4.5 6.0
- 55 to 25_C 6.0 15 30 35
v 85_C v 125_C
4.8 10 24 28 4.0 8.0 20 24
Unit Ui
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4)
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q (Figures 1 and 4)
160 105 32 27 150 100 30 26 140 90 28 24 60 27 12 10 10 15
200 145 40 34 190 125 38 33 175 120 35 30 75 32 15 13 10 15
240 190 48 41 225 150 45 38 210 140 42 36 90 36 18 15 10 15
ns
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5)
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to Q (Figures 2 and 5)
ns
tTLH, tTHL
Maximum Output Transition Time, any Output (Figures 1 and 4)
ns
Cin
Maximum Input Capacitance
pF pF
Cout
Maximum Three-State Output Capacitance, Output in High-Impedance State
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 24
CPD
Power Di i i C P Dissipation Capacitance (P E bl d O i (Per Enabled Output)* )*
pF F
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6
3-3
MOTOROLA
I II I I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I II I I I I I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I IIII I I I I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
MOTOROLA
MC54/74HC574A
Symbol S bl
tr, tf
tsu
tw
th
Maximum Input Rise and Fall Times
Minimum Pulse Width, Clock
Minimum Hold Time, Clock to Data
Minimum Setup Time, Data to Clock
Parameter P
Fig. Fi
1
1
3
3
3-4 VCC Volts 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.6 6.0 - 55 to 25_C Min 50 40 10 9.0 5.0 5.0 5.0 5.0 75 60 15 13 1000 800 500 400 Max Min 5.0 5.0 5.0 5.0 95 80 19 16 65 50 13 11
Guaranteed Limit
v 85_C
1000 800 500 400
Max
High-Speed CMOS Logic Data DL129 -- Rev 6 Min 110 90 22 19 5.0 5.0 5.0 5.0 75 60 15 13
v 125_C
1000 800 500 400 Max
Unit Ui
ns ns ns ns
MC54/74HC574A
SWITCHING WAVEFORMS
tr CLOCK 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tPHL Q tf VCC 1.3 V GND tPZL 1.3 V tPZH Q tPHZ 10% 90% tPLZ GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE 3.0 V
Figure 1.
Figure 2.
VALID VCC DATA 50% GND tsu CLOCK th VCC 50% GND D1 3 D0 2
EXPANDED LOGIC DIAGRAM
C Q D C Q D C Q D C Q D C Q D C Q D C Q D C Q D 11 1 19
Q0
18
Q1
Figure 3.
D2 TEST POINT D3 OUTPUT DEVICE UNDER TEST D4
4
17
Q2
5
16
Q3
6
15
Q4
CL*
D5 * Includes all probe and jig capacitance
7
14
Q5
Figure 4.
D6
8
13
Q6
TEST POINT OUTPUT DEVICE UNDER TEST 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
D7
9
12
Q7
CLOCK OUTPUT ENABLE
CL*
* Includes all probe and jig capacitance
Figure 5. Test Circuit
High-Speed CMOS Logic Data DL129 -- Rev 6
3-5
MOTOROLA
MC54/74HC574A
OUTLINE DIMENSIONS
J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E
B A F C L
DIM A B C D F G H J K L M N NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040
20 1
11 10
N H D
SEATING PLANE
G
K
J M
-A-
20 11
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
B
1
10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
-A-
20 11
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
10X
-B-
1 10
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
MOTOROLA
3-6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC574A
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High-Speed CMOS Logic Data DL129 -- Rev 6
3-7
MC74HC574A/D MOTOROLA

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